Compiler driven dynamic reconfiguration of architectural variants

Reconfigurable computing systems can change the functionality and structure of their components in order to improve the resource efficiency. Many existing architectures [73, 38] have to be programmed in assembly, or a related compiler does not provide full automation. Usually, a compiler is customized to a specific reconfigurable system developed for a certain application domain. This thesis presents a unified hardware/software approach called CoBRA1, where compilerdriven reconfiguration selects from a fixed set of modes known to the compiler. Such modes are denoted as reconfigurable architectural variants or briefly variants. Each variant relies on matching program analysis and represents optimal machine configurations for certain application domains. Typical optimization goals are a fast execution, small code size, or low power dissipation. The machine can be reconfigured by invoking special instructions between code using different configurations at run-time. A prominent example is to reconfigure between different parallelization paradigms like SIMD or MIMD. Given a program that exhibits both regular and non-regular structures, the compiler can determine the best execution mode by analyzing the parallelism. Reconfiguring the connections between ALUs and register banks at run-time allows to exploit more physical registers than architecturally available. In a multi-core, a processor can use registers of other processors temporarily to avoid spilling or communicate efficiently employing some registers in a shared manner. Using a manageable set of variants leads to an enormous reduction in the design space, compared to fine-grained reconfiguration. The compiler then addresses this finite design space efficiently by applying well-known program analysis techniques. Reconfiguration can be performed with very low effort at run-time by switching fixed, coarse-grained components like instruction decoders, ALUs and register banks. Much complexity like generating machine code and utilizing reconfiguration is hidden from the user in contrast to other reconfigurable approaches [73, 38]. Programming reconfigurable hardware in a sequential High-Level Language (HLL) such as C using a single tool avoids further manual effort and minimizes both time-to-market and error rates. This thesis concentrates on switching between SIMD and MIMD execution and reconfiguring register connections. In both cases, we present original methods to select variants and generate optimized machine code efficiently, or enhance existing approaches known from literature. Furthermore, we propose additional opportunities in reconfiguration, which may be part of future work. Our approach has been evaluated using a multi-core of four-tightly coupled processors, which can be simulated using a synthesized model or a cycle-accurate software simulator. Additionally, suchmodel can be mapped to a Field Programmable Gate Array (FPGA) based Compiler-Driven Dynamic Reconfiguration of Architectural Variants (merge two Ds to a B)